1. Field of the Invention
This invention relates to semiconductor devices, and in particular relates to semiconductor devices of the LGA (Land Grid Array) type, in which packages are reduced in sizes to be substantially identical to semiconductor chips. In addition, this invention relates to semiconductor devices of the LGA type in which packages are hardly separated from electrodes connected with external circuits by securing stability in soldering. Furthermore, this invention also relates to manufacturing methods for semiconductor devices of the LGA type.
This application claims priority on Japanese Patent Application No. 2003-44495, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, semiconductor devices are designed in such a way that semiconductor chips and their electrodes are integrally enclosed (or encapsulated) in resin packages, in which electrodes are partially exposed to the exterior. Conventionally, semiconductor devices are constituted such that electrodes thereof partially and horizontally project from prescribed sides of packages therefor, an example of which is disclosed in Japanese Patent Application Publication No. 2000-286375 (in particular, FIG. 2). To cope with the recent development and demand for downsizing packages and for increasing numbers of terminals extended outside of semiconductor chips, semiconductor devices of the so-called ‘LGA’ (Land Grid Array) type in which numerous electrodes are arranged in backsides (or mounting surfaces) of package housings are used.
A typical example of a semiconductor chip of the aforementioned LGA type is manufactured as follows:
FIG. 17 shows an example of a lead frame for use in manufacture of the conventional semiconductor device; and FIG. 18 is a cross sectional view showing essential parts of the semiconductor device that is manufactured using the lead frame.
A lead frame 105 shown in FIG. 17 comprises a terminal support member 151 (serving as an outer frame therefor), with which a plurality of inner terminals 102a are arranged internally, and a plurality of outer terminals 102b are arranged externally. In addition, a stage 152 is arranged at the center of the lead frame 105 and is supported by four stage supports 153 that are inwardly elongated from four corners of the lead frame 105.
A semiconductor chip 101 is mounted and fixed onto the stage 152 of the lead frame 105. When the semiconductor chip 101 is mounted in a face-up mode as shown in FIG. 18, pads 101a of the semiconductor chip 101 are connected with backsides of terminals 102 (representing the aforementioned terminals 102a and 102b) via connection fine lines 103. In contrast, when the semiconductor chip 101 is mounted in a face-down mode (not illustrated specifically), the pads 101a of the semiconductor chip 101 are directly connected with the terminals 102 via solder bumps or solder balls.
As described above, the semiconductor chip 101 and the lead frame 105 are connected and assembled together to form a lead frame assembly, which is enclosed (or encapsulated) in a resin package 104 in such a way that electrode surfaces 121 of the terminals 102 connected with an external circuit (not shown) are exposed to the exterior. Next, the electrode surfaces 121 of the terminals 102 and the prescribed parts of the terminal support member 151 exposed to the exterior of the resin package 104 are subjected to polishing and removal in dicing; thus, the inner terminals 102a are separated from the outer terminals 102b. Actually, the manufacturer uses the so-called multiple-connected lead frame assembly in which multiple units of lead frames are interconnected together. Therefore, outer peripheral portions of the outer terminals 102b are subjected to dicing, so that individual semiconductor devices are separated from each other. Reference symbol DG designates a cutting groove that is left after the terminal support member 151 is subjected to polishing and removal.
In the semiconductor device of the LGA type described above, the terminals 102 are partially extended outside of the semiconductor chip 102. For this reason, the overall size of the semiconductor device becomes bigger than the size of the semiconductor chip 101. This does not satisfy the aforementioned demand for downsizing the semiconductor device.
In order to establish connection between the aforementioned semiconductor device and an external circuit, the lower surface (or mounting surface) of the semiconductor device should be soaked into a solder bath so that fillets are formed at the electrodes 121 of the terminals 102 and are brought into tight contact with terminals of the external circuit. At this soldering, the conventional semiconductor device has the following problems.
That is, a terminal surface 123 is exposed to a cut surface 141 formed on the prescribed surface of the package 104, so that the ‘exposed’ terminal surface 123 is arranged to continuously join the electrode surface 121. Therefore, when the semiconductor device is soaked into the solder bath, solders are continuously formed around the terminal surface 123 continuously joining the electrode surface 121 as shown in FIG. 19A, which causes formation of solder fillets F extended continuously from the electrode surface 121. This causes the amount of solder adhered to the electrode surface 121 become variable; and this therefore causes unwanted dispersion regarding joining strength with the external circuit. In addition, the unstable consumption of solder may bring problems in production management. In soldering, a solder fillet F is elongated to form a bridge across the inner terminal 102a and the outer terminal 102b as shown in FIG. 19B. Alternatively, due to the excessive amount of solder being used, a solder bridge (or solder bridges) may be formed between terminals of the external circuit, which is joined with the semiconductor device. Furthermore, when the semiconductor device is pulled up after being joined with an external circuit 120 as shown in FIG. 19C, the terminals 102 are easy to separate from the package 104.
Actually, the joining strength between the terminal 102 and the package 104 is relatively weak because the terminal 102 is made of a metal, and the package 104 is made of a resin. This produces a possibility that unwanted separation between the terminal 102 and the package 104 may easy occur due to an impact caused by dicing. The aforementioned Japanese Patent Application Publication No. 2000-286375 discloses a solution to this problem, according to which as shown in FIG. 19D, a terminal support member (called a “coupling body” in the publication) is removed from the backside of a package so that terminals (or “connecting pieces”) 110 are individually separated from each other, wherein lead-in portions 124 are arranged on prescribed sides of the terminals 110 oppositely to the separated region between the terminals 110 in order to improve adhesion with the package (or a “resin enclosing body”). However, this solution cannot solve the aforementioned problems because the ‘exposed’ terminal surface of the terminal is still formed continuously with the electrode surface; hence, it is difficult to stabilize the amount of the solder fillet F adhered to the electrode surface and the like, and it is difficult to avoid occurrence of the formation of a bridge (or bridges) due to soldering. In addition, the aforementioned publication is silent in disclosing the formation of the lead-in portions 124 on the face-to-face sides of cut surfaces 141 located in the separated region between the terminals 110, which are individually separated from each other. This cannot make the joining strength between the terminal 110 and the package 104 sufficiently; therefore, when the semiconductor device is pulled up after being joined with the external circuit, it is very difficult to exclude the possibility of the occurrence of separation between the terminal 110 and the package 104.